Priority is claimed to Korean Patent Application No. 2003-90552 filed on Dec. 12, 2004 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Disclosure
The present disclosure relates to a memory device and a method of manufacturing the same, and more particularly, to a memory device and a method of manufacturing the same using a simplified process of making source and drain regions, thereby increasing the yield and performance of the memory device.
2. Description of the Related Art
The storage capacity of a semiconductor memory device is determined by the degree of integration that represents the number of memory cells per unit area. In general, a semiconductor memory device includes a plurality of memory cells that are connected via circuits. For instance, a memory cell of a dynamic random access memory (DRAM) is comprised of a transistor and a capacitor. Accordingly, it is required to reduce the size of the transistor and the capacitor so as to increase the integration of the semiconductor memory device.
The integration of the semiconductor memory device is closely related to a design rule applied to a manufacture process thereof. Thus, a stricter design rule must be applied to the manufacture process so as to increase the integration of the semiconductor memory device. In other words, since a process margin for a photolithography process or an etching process is insufficient, more precision for this process is required to manufacture a semiconductor memory device.
In this connection, new types of semiconductor memory devices that include a data storage device, such as a giant magneto resistance (GMR) structure or a tunneling magneto resistance (TMR) structure on a transistor, have been developed. The GMR and TMR structures are data storage devices that are differentiated from a capacitor of a conventional semiconductor memory device.
A polysilicon-oxide-nitride-oxide-silicon (SONOS) memory device is one of the new types of semiconductor memory devices. FIGS. 1A through 1H illustrate a conventional method of fabricating the SONOS memory device.
Referring to FIG. 1A, a tunneling oxide layer 12, a nitride layer 13, a blocking oxide layer 14, and a gate electrode layer 15 are sequentially deposited on a semiconductor substrate 11, thus forming a gate stack structure. In this disclosure, the tunneling oxide layer 12, the nitride layer 13, and the blocking oxide layer 14 will be referred to as an oxide-nitride-oxide (ONO) layer. The ONO layer, which is a gate stack structure, must be etched to obtain source and drain regions 17a and 17b (refer to FIG. 1F) and a gate structure. For etching, a mask layer 16 and an electron beam resist 19 are sequentially applied onto a resultant structure, and the electron beam resist 19 is patterned, as shown in FIG. 1A. Next, the mask layer 16 and the gate electrode layer 15 are etched to obtain the structure of FIG. 1B. Next, the ONO layer is etched and the electron beam resist 19 is removed, thus obtaining the gate structure of FIG. 1C.
Next, as shown in FIG. 1D, an n-type dopant is implanted into the semiconductor substrate 11 to form the source and drain regions 17a and 17b. In this case, it is important to precisely control the concentration and thickness of the n-type dopant to prevent channel regions under the tunneling oxide layer 12 from being doped with the n-type dopant. Next, an insulating material is applied onto the semiconductor substrate 11 and both ends of the applied insulating material are etched to obtain the resultant structure of FIG. 1E. More specifically, the insulating layer is etched such that it is formed along the sidewalls of the gate stacked structure as a sidewall layer 18 and regions for the source and drain regions 17a and 17b are exposed. Next, as shown in FIG. 1F, the n-type dopant is further implanted into the regions for the source and drain regions 17a and 17b so as to control the amount of dopant therein and form the regions in desired shapes. Thereafter, annealing is performed on the resultant structure shown in FIG. 1G, thus activating the source and drain regions 17a and 17b. Then, as shown in FIG. 1H, a protective layer 19 is formed on the resultant structure, and a metallization process is performed to form an electrode layer 20 to interconnect the source and drain regions 17a and 17b and the gate electrode layer 15. Later, the electrode layer 20 can be patterned to form the appropriate electrode structure.
A conventional method of fabricating the SONOS memory device, such as that shown in FIGS. 1A through 1H, has the following problems. First, this method is complicated to execute. Namely, a gate electrode layer, which is formed of polysilicon, for example, is etched; an ONO layer is etched; an n-type dopant is implanted; a sidewall layer is deposited and etched; the n-type dopant is further implanted; and annealing is performed on the resultant structure.
Second, a channel region under an oxide layer must be formed to be narrow enough to form a gate stack structure to a width of 100 nm or less and obtain source and drain regions suitable for the gate stack structure. However, since the width of the gate stack structure is narrow, the distance between the source and drain regions may surely become extremely narrow during annealing after the implantation of the n-type dopant, thereby causing the source and drain regions to merge together. Accordingly, more precision for the method is required.
Third, it is difficult to completely etch a tunneling oxide layer since it is formed to a thin thickness of about 20 nm. Thus, it is difficult to implant the n-type dopant into a semiconductor substrate to a desired concentration.
Fourth, a pattern profile must be formed at an angle of about 90 degrees so as to make the distance between the source and drain regions be 100 nm or less. However, in this case, a mask layer must be formed to a thin thickness such that its profile can hardly be affected by the profile of an etching material. Depending on etching conditions, the mask layer may also be etched during the etching the ONO layer after etching the gate electrode layer, thereby remarkably deteriorating the profile of the mask layer. Deterioration of the mask layer profile increases the distance between the source and drain regions, and as a result, it is impossible to obtain any particular effect even if the n-type dopant is implanted into the semiconductor substrate to control the concentration and depth of the source and drain regions.